Normal view MARC view ISBD view

Modelling,Synthesis,and Rapid Prototyping with the VERILOG HDL

Michael D.Ciletti

Modelling,Synthesis,and Rapid Prototyping with the VERILOG HDL - New Delhi Pearson 2010 - xxii,727p,: Book

ISBN: 9788131732564

Subjects--Topical Terms:
VHDL--Electronics and Communication Engineering

Dewey Class. No.: 621.392

Place hold
Print
Add to your cart (remove)
Save record
BIBTEX Dublin Core MARCXML MARC (non-Unicode/MARC-8) MARC (Unicode/UTF-8) MARC (Unicode/UTF-8, Standard) MODS (XML) RIS ISBD
More searches

Search for this title in:
Other Libraries (WorldCat) Other Databases (Google Scholar) Online Stores (Bookfinder.com) Open Library (openlibrary.org)

Modelling,Synthesis,and Rapid Prototyping with the VERILOG HDL

Visitor Number: