Writing Testbenches : Functional Verification of HDL Models

Bergeron, Janick

Writing Testbenches : Functional Verification of HDL Models / Janick Bergeron - 1st Ed. - New York Springer Science+Business Media, LLC 2000 - xxii, 354p. : ill. ; 23cm

It includes Index Pages.

9781475783445


Integrated circuits—Verification; Verilog (Computer hardware description language); Computer hardware description languages; System safety; Systems engineering; Computer engineering; Computer-aided design; Engineering

621.392 BER

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