Writing Testbenches using SystemVerilog / (Record no. 26891)

MARC details
000 -LEADER
fixed length control field 02280nam a22001937a 4500
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20210203153828.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 200303b ||||| |||| 00| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781441939784
040 ## - CATALOGING SOURCE
Transcribing agency VITAP
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Edition number 23rd
Classification number 621.392 BER
100 ## - MAIN ENTRY--PERSONAL NAME
9 (RLIN) 8884
Personal name Bergeron, Janick
245 ## - TITLE STATEMENT
Title Writing Testbenches using SystemVerilog /
Statement of responsibility, etc. Janick Bergeron
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. New York, USA
Name of publisher, distributor, etc. Springer Science+Business Media, Inc.
Date of publication, distribution, etc. 2010
300 ## - PHYSICAL DESCRIPTION
Extent xxvi, 411p. : ill. ;
Dimensions 24cm
500 ## - GENERAL NOTE
General note It includes Appendix, Glossary and Index<br/>Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology.<br/><br/>Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all.<br/><br/>Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model.<br/><br/>Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog.<br/><br/>
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
9 (RLIN) 8882
Topical term or geographic name entry element Integrated circuits—Verification; Verilog (Computer hardware description language); Computer hardware description languages; System safety; Systems engineering; Computer engineering; Computer-aided design; Engineering
856 ## - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="https://www.springer.com/in/book/9780387292212#aboutBook">https://www.springer.com/in/book/9780387292212#aboutBook</a>
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Reference Book
Classification part 621.392 BER
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Materials specified (bound volume or other part) Damaged status Use restrictions Not for loan Collection code Home library Current library Shelving location Date acquired Source of acquisition Cost, normal purchase price Inventory number Total Checkouts Full call number Barcode Date last seen Date last checked out Price effective from Koha item type Public note
    Dewey Decimal Classification Paper Back   Restricted Access Not For Loan Reference School of Electronics Section VIT-AP General Stacks 2020-02-28 Bookionics 11592.05 VJ/45624 1 621.392 BER 019151 2021-08-18 2021-02-03 2020-03-03 Reference Book ECE

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