MARC details
| 000 -LEADER |
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| fixed length control field |
02452nam a22002057a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200303144411.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
200303b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9781475776294 |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
VITAP |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Edition number |
23rd |
| Classification number |
621.3815 BHA |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| 9 (RLIN) |
8888 |
| Personal name |
Bhatnagar, Himanshu |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
Advanced ASIC Chip Synthesis : |
| Remainder of title |
using Synopsys Design Compiler, Physical Compiler and Prime Time / |
| Statement of responsibility, etc. |
Himanshu Bhatnagar |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
2nd Ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
New York |
| Name of publisher, distributor, etc. |
Springier Science+Business Media, LLC |
| Date of publication, distribution, etc. |
2002 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxv, 328p. : ill. ; |
| Dimensions |
24cm |
| 500 ## - GENERAL NOTE |
|---|
| General note |
It includes Appendix and Index Pages <br/>Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.<br/>The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.<br/>Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| 9 (RLIN) |
8890 |
| Topical term or geographic name entry element |
Compilers (Computer programs); Logic design--Data processing; Application-specific integrated circuits--Computer-aided design; Systems engineering; Computer-aided design; Engineering; Computer engineering; Logic design |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
<a href="https://www.springer.com/in/book/9780792376446">https://www.springer.com/in/book/9780792376446</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Reference Book |
| Classification part |
621.3815 BHA |
