Course reserves for HDL Verification and Methodology
- Department: Electronics
- Course number: ECE3006
- Instructors:
| Title | Author | Item type | Location | Collection | Call number | Copy number | Status | Date due | Notes | Link | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Writing Testbenches : Functional Verification of HDL Models / | Bergeron, Janick | Text Book | VIT-AP General Stacks |
621.392 BER | In transit from VIT-AP to School of Electronics Section since 2024-02-22 | ECE | Record URL | ||||
| System Verilog for Verification : | Spear, Chris | Reference Book | VIT-AP General Stacks |
Reference | 621.392 SPE | Not For Loan (Restricted Access) | ECE | Record URL | |||
| Hardware Verification with SystemVerilog : | Mintz, Mike | Reference Book | VIT-AP General Stacks |
621.392 MIN | Not For Loan (Restricted Access) | ECE | Record URL | ||||
| Formal Verification An Essential Toolkit for modern VLSI Design / | Seligman, Erik | Reference Book | VIT-AP General Stacks |
Reference | 621.381548 SEL | Not For Loan (Restricted Access) | ECE | Record URL |