| Item type | Current library | Call number | Materials specified | Status | Notes | Barcode | Course reserves | |
|---|---|---|---|---|---|---|---|---|
| Reference Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | Not for loan | ECE | 018454 | ||
| Text Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | Available | ECE | 018455 | ||
| Text Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | Available | ECE | 018456 | ||
| Text Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | Available | ECE | 018457 | ||
| Text Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | Available | ECE | 018458 | ||
| Text Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | In transit from VIT-AP to School of Electronics Section since 2025-09-23 | ECE | 018459 | ||
| Text Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | Available | ECE | 018460 | ||
| Text Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | In transit from VIT-AP to School of Electronics Section since 2024-01-31 | ECE | 018461 | ||
| Text Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | Available | ECE | 018462 | ||
| Text Book | VIT-AP General Stacks | 621.382 KEA (Browse shelf(Opens below)) | Paper Back | Available | ECE | 018463 |
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| 621.382 HSU Schum's Outlines Analog and Digital Communications / | 621.382 HSU Schum's Outlines Analog and Digital Communications / | 621.382 HSU Schum's Outlines Analog and Digital Communications / | 621.382 KEA The Simple Art of SoC Design: | 621.382 KEA The Simple Art of SoC Design: | 621.382 KEA The Simple Art of SoC Design: | 621.382 KEA The Simple Art of SoC Design: |
Includes appendix and index
The Challenges of Complex Design; Simplifying RTL Design; Reducing Complexity in Control-Dominated Designs; Hierarchical State Machines; More on State Space; Verification; Reducing Complexity in Data Path Dominated Designs; Simplifying Interfaces; Complexity at the Chip Level; Raising Abstraction Above RTL; SystemVerilog Extensions; The Future of Design.
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