TY  - BOOK
AU  - Michael D.Ciletti
TI  - Modelling,Synthesis,and Rapid Prototyping with the VERILOG HDL
SN  - 9788131732564
U1  - 621.392 23rd
PY  - 2010///
CY  - New Delhi
PB  - Pearson 
KW  - VHDL
KW  - Electronics and Communication Engineering
ER  -