Bergeron, Janick <br/><br/>
Writing Testbenches  : Functional Verification of HDL Models 
/ Janick Bergeron 
 - 1st Ed. 
 - New York  Springer Science+Business Media, LLC  2000 
 - xxii, 354p. : ill. ; 23cm 
<br/><br/> It includes Index Pages. 
<br/><br/><label>ISBN: </label>9781475783445 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits—Verification; Verilog (Computer hardware description language); Computer hardware description languages; System safety; Systems engineering; Computer engineering; Computer-aided design; Engineering
<br/><br/><label>Dewey Class. No.: </label>621.392 BER