000			00298nam a2200121Ia 4500
999			_c15168 _d15168
003			OSt
005			20180201103656.0
008			170725s9999 xx 000 0 und d
020			_a9788131732564
040			_cVITAP
041			_aEnglish
082			_223rd _a621.392
100			_aMichael D.Ciletti _91826
245		0	_aModelling,Synthesis,and Rapid Prototyping with the VERILOG HDL
260			_bPearson _aNew Delhi _c2010
300			_bBook _axxii,727p,:
650		0	_91827 _aVHDL _xElectronics and Communication Engineering
942			_cBK _2ddc