000			00603nam a22001937a 4500
999			_c24936 _d24936
003			VITAP
005			20190111122129.0
008			190111b ||||| |||| 00| 0 eng d
020			_a9780070252219
040			_cVITAP
082			_223rd ed. _a621.392
100			_94627 _aZainalabedin Navabi
245			_aVerilog Digital System Design: _bRegister Transfer Level Synthesis, Testbench, and Verification
250			_a2nd ed.
260			_aNew Delhi _bMcGraw Hill Education (India) Private Limited _c2014
300			_axvi, 384p. _eWith CD
500			_aIt includes index, glossary.
942			_2ddc _cREF