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| 005 | 20200311152552.0 | ||
| 008 | 200311b ||||| |||| 00| 0 eng d | ||
| 020 | _a9781461350125 | ||
| 040 | _cVITAP | ||
| 082 |
_223rd _a621.392 BER |
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| 100 |
_99378 _aBergeron, Janick |
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| 245 |
_aWriting Testbenches : Functional Verification of HDL Models / _cJanick Bergeron |
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| 250 | _a2nd ed. | ||
| 260 |
_aNetherland _bSpringer _c2003 |
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| 300 |
_axxx, 475p. : ill. ; _c24cm |
||
| 500 | _aIt includes Appendix, Glossary, Afterwords and Index Pages. mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification. | ||
| 650 | 0 |
_99393 _aComputer hardware description languages; Integrated circuits—Verification; Systems engineering; Computer-aided design; Engineering; Computer engineering; Computer science; Electrical engineering |
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| 856 | _uhttps://www.springer.com/gp/book/9781402074011 | ||
| 942 |
_2ddc _cBK _h621.392 BER |
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