| 000 -LEADER |
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| fixed length control field |
02269nam a22001937a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200312103901.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
200205b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9783319594170 |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
VITAP |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Edition number |
23rd |
| Classification number |
621.3815 MEH |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| 9 (RLIN) |
7996 |
| Personal name |
Mehta, Ashok B. |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
ASIC/SoC Functional Design Verification : |
| Remainder of title |
A Comprehensive Guide to Technologies and Methodologies / |
| Statement of responsibility, etc. |
Ashok B. Meheta |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Netherland |
| Name of publisher, distributor, etc. |
Springer International Publishing AG |
| Date of publication, distribution, etc. |
2018 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxxi, 328p. : ill. ; |
| Dimensions |
24cm |
| 500 ## - GENERAL NOTE |
|---|
| General note |
It includes bibliography and index pages<br/><br/>Introduction<br/>This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.<br/>Keywords<br/>System-on-Chip design System-on-Chip verification Functional hardware verification SystemVerilog Assertions SystemVerilog Functional Coverage Assertion Based Verifiction |
| 653 ## - INDEX TERM--UNCONTROLLED |
|---|
| Uncontrolled term |
Logic design; Microprocessors; Electronic circuits; Integrated circuits—Verification; SystemVerilog (Computer hardware description language); Application-specific integrated circuits—Design; Systems on a chip--Design and construction |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
<a href="https://link.springer.com/book/10.1007/978-3-319-59418-7">https://link.springer.com/book/10.1007/978-3-319-59418-7</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Reference Book |
| Classification part |
621.3815 MEH |
