| 000 -LEADER |
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| fixed length control field |
01995nam a22002057a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20200311152552.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
200311b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9781461350125 |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
VITAP |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Edition number |
23rd |
| Classification number |
621.392 BER |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| 9 (RLIN) |
9378 |
| Personal name |
Bergeron, Janick |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
Writing Testbenches : Functional Verification of HDL Models / |
| Statement of responsibility, etc. |
Janick Bergeron |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Netherland |
| Name of publisher, distributor, etc. |
Springer |
| Date of publication, distribution, etc. |
2003 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxx, 475p. : ill. ; |
| Dimensions |
24cm |
| 500 ## - GENERAL NOTE |
|---|
| General note |
It includes Appendix, Glossary, Afterwords and Index Pages.<br/><br/>mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.<br/><br/> |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| 9 (RLIN) |
9393 |
| Topical term or geographic name entry element |
Computer hardware description languages; Integrated circuits—Verification; Systems engineering; Computer-aided design; Engineering; Computer engineering; Computer science; Electrical engineering |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
<a href="https://www.springer.com/gp/book/9781402074011">https://www.springer.com/gp/book/9781402074011</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Text Book |
| Classification part |
621.392 BER |
