| 000 -LEADER |
|---|
| fixed length control field |
02262nam a22002177a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20200311154337.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
200311b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780128007273 |
| 040 ## - CATALOGING SOURCE |
|---|
| Transcribing agency |
VITAP |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Edition number |
23rd |
| Classification number |
621.381548 SEL |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| 9 (RLIN) |
9379 |
| Personal name |
Seligman, Erik |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
Formal Verification An Essential Toolkit for modern VLSI Design / |
| Statement of responsibility, etc. |
Erik Seligman,Tom Schubert and M. V. Achutha Kiran Kumar |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
USA |
| Name of publisher, distributor, etc. |
Morgan Kauffman |
| Date of publication, distribution, etc. |
2015 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xvii,353p,: |
| 500 ## - GENERAL NOTE |
|---|
| General note |
It includes Index Pages<br/><br/>Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of SystemVerilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity.<br/><br/>Key Features<br/>Learn formal verification algorithms to gain full coverage without exhaustive simulation<br/>Understand formal verification tools and how they differ from simulation tools<br/>Create instant test benches to gain insight into how models work and find initial bugs<br/>Learn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems<br/> |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| 9 (RLIN) |
9380 |
| Topical term or geographic name entry element |
Verilog (Computer hardware description language); Electronic circuits--Testing; Integrated circuits--Very large scale integration--Design and construction; Electronic circuits; Integrated circuits; Engineering |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| 9 (RLIN) |
9381 |
| Personal name |
Schubert,Tom |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| 9 (RLIN) |
9395 |
| Personal name |
Kumar, M. V. Achutha Kiran |
| 856 ## - ELECTRONIC LOCATION AND ACCESS |
|---|
| Uniform Resource Identifier |
<a href="https://www.elsevier.com/books/formal-verification/seligman/978-0-12-800727-3">https://www.elsevier.com/books/formal-verification/seligman/978-0-12-800727-3</a> |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Reference Book |
| Classification part |
621.381548 SEL |
