ASIC/SoC Functional Design Verification : A Comprehensive Guide to Technologies and Methodologies / Ashok B. Meheta
By: Mehta, Ashok B.
Material type: TextPublisher: Netherland Springer International Publishing AG 2018Description: xxxi, 328p. : ill. ; 24cm.ISBN: 9783319594170.Subject(s): Logic design; Microprocessors; Electronic circuits; Integrated circuits—Verification; SystemVerilog (Computer hardware description language); Application-specific integrated circuits—Design; Systems on a chip--Design and constructionDDC classification: 621.3815 MEH Online resources: Click here to access onlineItem type | Current location | Call number | Status | Notes | Date due | Barcode | Course reserves |
---|---|---|---|---|---|---|---|
Text Book | School of Electronics Section General Stacks | 621.3815 MEH (Browse shelf) | In transit from VIT-AP to School of Electronics Section since 2024-04-04 | ECE | 019202 | ||
Text Book | VIT-AP General Stacks | 621.3815 MEH (Browse shelf) | Checked out to MADHU KIRAN (23MVD7017) | ECE | 2024-05-18 | 019203 | |
Text Book | School of Electronics Section General Stacks | 621.3815 MEH (Browse shelf) | In transit from VIT-AP to School of Electronics Section since 2024-04-06 | ECE | 019204 | ||
Text Book | VIT-AP General Stacks | 621.3815 MEH (Browse shelf) | Checked out to SHARMILA SAHA (23MVD7004) | ECE | 2024-05-16 | 019205 | |
Text Book | VIT-AP General Stacks | 621.3815 MEH (Browse shelf) | Checked out to P Siva Ramakrishna (70422) | ECE | 2024-07-04 | 019206 | |
Text Book | School of Electronics Section General Stacks | 621.3815 MEH (Browse shelf) | In transit from VIT-AP to School of Electronics Section since 2024-05-06 | ECE | 019207 | ||
Text Book | VIT-AP General Stacks | 621.3815 MEH (Browse shelf) | Available | ECE | 019208 | ||
Text Book | VIT-AP General Stacks | 621.3815 MEH (Browse shelf) | Checked out to Chandan Kumar Pandey (70155) | ECE | 2024-10-03 | 019209 | |
Text Book | VIT-AP General Stacks | 621.3815 MEH (Browse shelf) | Checked out to DAYANAND KALAPALA (23PHD7118) | ECE | 2024-08-28 | 019210 | |
Reference Book | VIT-AP General Stacks | 621.3815 MEH (Browse shelf) | Not For Loan (Restricted Access) | ECE | 019009 |
It includes bibliography and index pages
Introduction
This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon The author outlines all of the verification sub-fields at a high level, with just enough depth to allow a manager/decision maker or an engineer to grasp the field which can then be pursued in detail with the provided references. He describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
Keywords
System-on-Chip design System-on-Chip verification Functional hardware verification SystemVerilog Assertions SystemVerilog Functional Coverage Assertion Based Verifiction
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