Advanced ASIC Chip Synthesis : using Synopsys Design Compiler, Physical Compiler and Prime Time / Himanshu Bhatnagar
By: Bhatnagar, Himanshu.
Material type: TextPublisher: New York Springier Science+Business Media, LLC 2002Edition: 2nd Ed.Description: xxv, 328p. : ill. ; 24cm.ISBN: 9781475776294.Subject(s): Compilers (Computer programs); Logic design--Data processing; Application-specific integrated circuits--Computer-aided design; Systems engineering; Computer-aided design; Engineering; Computer engineering; Logic designDDC classification: 621.3815 BHA Online resources: Click here to access onlineItem type | Current location | Collection | Call number | Status | Notes | Date due | Barcode | Course reserves |
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Text Book | School of Electronics Section General Stacks | 621.3815 BHA (Browse shelf) | In transit from VIT-AP to School of Electronics Section since 2024-02-08 | ECE | 019211 | |||
Text Book | VIT-AP General Stacks | 621.3815 BHA (Browse shelf) | Checked out to MADHU KIRAN (23MVD7017) | ECE | 2024-05-23 | 019212 | ||
Text Book | VIT-AP General Stacks | 621.3815 BHA (Browse shelf) | Checked out to G D V Santhosh Kumar (70563) | ECE | 2024-07-21 | 019214 | ||
Text Book | School of Electronics Section General Stacks | 621.3815 BHA (Browse shelf) | In transit from VIT-AP to School of Electronics Section since 2024-02-20 | ECE | 019215 | |||
Text Book | VIT-AP General Stacks | 621.3815 BHA (Browse shelf) | Available | ECE | 019216 | |||
Text Book | VIT-AP General Stacks | 621.3815 BHA (Browse shelf) | Available | ECE | 019217 | |||
Text Book | VIT-AP General Stacks | 621.3815 BHA (Browse shelf) | Checked out to HIMADRI TRIPATHI (23MVD7012) | ECE | 2024-05-24 | 019218 | ||
Text Book | VIT-AP General Stacks | 621.3815 BHA (Browse shelf) | Checked out to SHARMILA SAHA (23MVD7004) | ECE | 2024-05-14 | 019219 | ||
Text Book | School of Electronics Section General Stacks | 621.3815 BHA (Browse shelf) | In transit from VIT-AP to School of Electronics Section since 2024-01-27 | ECE | 019213 | |||
Reference Book | VIT-AP General Stacks | Reference | 621.3815 BHA (Browse shelf) | Not For Loan (Restricted Access) | ECE | 019153 |
It includes Appendix and Index Pages
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® Physical Compiler® and PrimeTime®, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail.
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.
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